The current state of the art of semiconductor development is the mass production of large integrated circuits “IC's” containing several million active components. One type of device fitting this description is a large Field Programmable Gate Array “FPGA.” FPGAs and other devices may operate at speeds of several hundred Megahertz and it is not unusual that these integrated circuits include over a thousand pins that bring high speed signals into and out of the integrated circuit die. With a large number of active internal components switching at high speeds, these devices consume large amounts of power. Therefore it is necessary to have a packaging solution that allows for the distribution of over a thousand high speed signal lines and also provides for a plurality of connections to supply power to the device. To solve this problem for a single FPGA, IC designers have used a technique wherein thousands of “bumps” are distributed over the surface of the FPGA via thick metal lines. It would not be unusual to have two-thousand bumps for power and another two thousand for ground. The large number of bumps reserved for power ensures only a minimal resistive drop from the surface of the device to the active devices within the FPGA.
The power and signal connections extend from the bumps present on the surface of the FPGA to balls of a Ball-Grid-Array “BGA” package. A BGA utilized for packaging a large FPGA has approximately 1500 balls; 1000 for input and output “I/O” connections and 500 for power and ground connections. Power is supplied to the balls of the BGA package through thick metal conductors to the bumps present on the surface of the FPGA. A drawing of a BGA package is shown in FIG. 1 (Prior Art). A plurality of bond bumps 3 are shown disposed between FPGA die 5 and package PCB 1. Array of bond balls 2 are shown attached to a lower surface of the package PCB 1 and are coupled to bond bumps 3 of FPGA die 5 with conductors within the PCB (not shown). The array of bond balls 2 are used to connect the BGA package to a system containing several similar devices and other components. Bond bumps 3 are attached to solder reflowable bond pads (not shown) on the package PCB 1. The bond pads are then connected layers of interconnect metal within the package PCB. The bond bumps 3 and bond pads are made of materials selected to provide sufficient electrical and mechanical contact between FPGA integrated circuit die 5 and the package PCB 1. For instance bond bumps 3 may be made of an alloy containing tin and lead. The package PCB may be an FR4 type circuit board constructed of woven glass and epoxy. Because the FPGA die may consume large amounts of power during operation, the mechanical connection will be subjected to stress and potential electrical failure from temperature changes caused by power dissipation in the FPGA die and other devices. For example, the coefficient of linear thermal expansion for the FR4 type PCB 1 is approximately eleven parts per million per degree Centigrade “ppm/° C.” The same coefficient for silicon of the FPGA die is three ppm/° C. Because of this disparity, it is possible for the linear expansion to cause electrical conductors in FPGA die 5 to delaminate from the silicon substrate of FPGA die 5. Furthermore, thermal cycling may cause grain growth in bond bumps 3 and may increase the likelihood of voids and cracks developing within bond bumps 3. The presence of voids or cracks is likely to cause a decrease in electrical conductivity or failure of continued electrical and mechanical contact between FPGA die 5 and package printed circuit board 1.
In an electrical system containing several FPGA die and other components, multiple levels of assembly may be required. The BGA package of FIG. 1 and other devices may be assembled to a larger system-level printed circuit board which may further be a component of an even larger system. To interconnect each level of assembly, the system temperature is increased to the melting point of the solder balls or solder bumps between components. Repeated high temperature cycling of the components can fatigue the materials present in the PCB's. One approach to solve this problem is to lower the temperature by providing a solder ball with a lower melting point. U.S. Pat. No. 6,379,982 discloses one of these structures and is shown in FIG. 2.
FIG. 2 is a cross-sectional drawing of a solder ball 13, a low melting point metal layer 11, bond pad 12, integrated circuit “IC” chip interconnect 16, and substrate 15. Solder ball 13 is a reflowed high melt (ninety-seven percent lead and three percent tin) solder ball that is positioned above bond bad 12. Bond pad 12 is a solder wettable pad that makes contact through a via to IC chip interconnect 16 which is a copper trace disposed within conventional substrate 15 and covered by passivation layer 17. Low melting point layer 11 is a low melting point metal such as tin, bismuth, indium, or alloys of these materials and is disposed upon solder ball 13. When the interconnect structure of FIG. 2 is subjected to a low temperature joining cycle, a volume of eutectic alloy is formed atop the solder ball 13. When subjected to additional eutectic temperature cycles, the volume of eutectic alloy melts and forms a structure with improved thermal fatigue resistance and also allows for easy removal of the IC chip for the purpose of testing or replacement.
A semiconductor substrate has also been invented as a solution to failures caused by devices manufactured on substrate materials with disparate coefficients of linear expansion and is shown in FIG. 3. FIG. 3 shows a semiconductor substrate 9 and a plurality of FPGA dice 5-8 disposed on semiconductor substrate 9. Arrays of bond bumps 3 are disposed between FPGA dice 5-9 and semiconductor substrate 9. The bond bumps 3 mechanically and electrically connect FPGA dice 5-9 to semiconductor substrate 9. Because the FPGA die and the semiconductor substrate 9 are both capable of being constructed from a silicon substrate, the coefficients of linear expansion are approximately equal. Thus the likelihood of failure caused by materials having disparate coefficients of linear expansion is reduced.
FIG. 4 is a cross-sectional drawing of the semiconductor substrate 9 of FIG. 3. An interconnect structure 20 containing a “thin conductor layers portion” 22 characterized as having a plurality of thin fine-pitch conductors is disposed onto a “power connection structure” 30. A plurality of thick horizontal conductors is disposed within a “thick conductor layers portion” 31 within power connection structure 30 and a plurality of through-holes extends vertically through a semiconductor power through-hole portion 32 within the power connection structure 30. These thick horizontal conductors present within the power connection structure 30 are of a thickness of approximately two microns or greater. A conductive via is disposed within each through-hole. An example of a through-hole containing a conductive via 33 is shown disposed within the semiconductor power through-hole portion 32. A plurality of bonding bumps 3 is disposed upon the thin conductor layers portion 22. The bond bumps are arrayed to match the corresponding array of die bond pads 24 present on the FPGA dice 5-8 of FIG. 3. The bond bumps conduct power to the FPGA dice through vertical vias within through-holes of the power connection structure 30 to thick horizontal conductive layers present within the thick conductor layers portion 31. The thick conductor layers are then electrically coupled to a thick conductor layer present on the bottom plane of the semiconductor power through-hole portion by the conductive vias disposed within the semiconductor power through-hole portion 32. In this manner, a large amount of current required by the FPGA devices is conducted vertically through the power connection structure 30 to thick conductors within the thick conductor layers portion 31 to vias extending through the interconnect structure 20 to the bond pads 24 and then to bond bumps 23 that interface to the power connections on the surface of FPGA dice 5-8 of FIG. 3. This provides for low resistance power connections through the substrate while simultaneously allowing the maximum density of thin fine-pitch conductor interconnects within the interconnect structure 20 for routing signals between the plurality of FPGA dice 5-8 of FIG. 3 disposed on semiconductor substrate 9.
The semiconductor substrate 9 of FIG. 4 may be constructed by coupling portions manufactured by disparate processing techniques. For example, thin conductor layers portion 22 may be constructed by traditional wet-etch processing methods. Furthermore, power connection structure 30 may be processed using traditional dry-etch processing methods. Once thin conductor layers portion and thick conductor layers portion 32 are processed they can be joined together by fusion bonding the two structures. Fusion bonding permits the planar surfaces of interconnect structure 20 and power connection structure 30 to contact each other physically within atomic dimensions such that direct bonds exist between the two structures obviating any need for adhesive material between the two structures. In other embodiments, interconnect structure 20 and power connection structure 30 are connected through the use of adhesive materials between the structures.
The semiconductor substrate 9 supports routing signal connections between a plurality of semiconductor ICs with thin, fine-pitch conductors and conduction of power to the semiconductor ICs through thick conductors with large feature sizes. However it is necessary to make power connections to the semiconductor substrate 9. It is also necessary to route signals to and from FPGA dice 5-9 from other components not located on the same semiconductor substrate. One method of making power connections and signal connections to the semiconductor substrate is with Shin-Etsu conductive elastomeric connectors from Shin-etsu Polymer Co., Ltd. However, these connectors have a higher profile than solder balls, cost more to manufacture than solder balls, and are not as fine in pitch as those allowed with solder ball interconnections. Another possible method of making power connections is to connect large copper bus bars to the backside of the semiconductor substrate 9. However, a large thick bar of copper has disparate coefficients of linear expansion compared to semiconductor substrate 9 and thus delamination of the copper layers of power connection structure 30 from semiconductor substrate 9 may occur. Furthermore, a semiconductor substrate is not a suitable substrate for supporting the multiple types of components that are also part of the system. These components include: fiber-optic connectors, crystal oscillators, voltage regulators, and other types of components and connectors. In addition, the aforementioned connections means are not easily removed without destroying the semiconductor substrate if semiconductor substrate 9 requires rework or additional testing.
A substrate capable of connection to a semiconductor substrate is therefore desired which allows 1) robust mechanical and electrical connection; 2) interfacing to thousands of high density IC chip interconnections; 3) low resistance conductors capable of supporting high current, power connections; 4) mounting of physical connectors and a variety of electrical components; and 5) nondestructive detachment for test or qualification of the semiconductor substrate.